IEEE Transactions on Computers
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Genetic Algorithms Plus Data Structures Equals Evolution Programs
Genetic Algorithms Plus Data Structures Equals Evolution Programs
Genetic Algorithms
Stochastic activity networks: formal definitions and concepts
Lectures on formal methods and performance analysis
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
The Möbius Framework and Its Implementation
IEEE Transactions on Software Engineering
A New Functional Fault Model for FPGA Application-Oriented Testing
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Minimizing the Number of Test Configurations for Different FPGA Families
ATS '99 Proceedings of the 8th Asian Test Symposium
Analyzing the Test Generation Problem for an Application-Oriented Test of FPGAs
ETW '00 Proceedings of the IEEE European Test Workshop
Testing memory modules in SRAM-based configurable FPGAs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
Automatic Test Program Generation: A Case Study
IEEE Design & Test
Code Generation for Functional Validation of Pipelined Microprocessors
Journal of Electronic Testing: Theory and Applications
Fully Automatic Test Program Generation for Microprocessor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing)
Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing)
Application-dependent testing of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SMART And FAST: Test Generation for VLSI Scan-Design Circuits
IEEE Design & Test
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
FPGA Based High Date Rate Radio Interfaces for Aerospace Wireless Sensor Systems
ICONS '09 Proceedings of the 2009 Fourth International Conference on Systems
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Reliable Railway Station System Based on Regular Structure Implemented in FPGA
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Genetic algorithm for test pattern generator design
Applied Intelligence
FPGA Architecture
Application Dependent FPGA Testing Method
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
EWDTS '10 Proceedings of the 2010 East-West Design & Test Symposium
SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Failure Probability and Fault Observability of SRAM-FPGA Systems
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
Coverage-Directed Test Generation Automated by Machine Learning -- A Review
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evolutionary algorithm parameter tuning with sensitivity analysis
SIIS'11 Proceedings of the 2011 international conference on Security and Intelligent Information Systems
No free lunch theorems for optimization
IEEE Transactions on Evolutionary Computation
Fuzzy clustering with partial supervision
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A genetic algorithm framework for test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimized reseeding by seed ordering and encoding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SEU-X: A SEu un-excitability prover for SRAM-FPGAs
IOLTS '12 Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012)
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Testing of FPGAs is gaining more and more interest because of the application of FPGA devices in many safety-critical systems. We propose GABES, a tool for the generation of test patterns for application-dependent testing of SEUs in SRAM-FPGAs, based on a genetic algorithm. Test patterns are generated and selected by the algorithm according to their fault coverage: Faults are injected in a simulated model of the circuit, the model is executed for each test pattern and the respective fault coverage is computed. We focus on SEUs in configuration bits affecting logic resources of the FPGA. This makes our fault model much more accurate than the classical stuck-at model. Results from the application of the tool to some circuits from the ITC'99 benchmarks are reported. These results suggest that this approach may be effective in the inspection of safety-critical components of control systems implemented on FPGAs.