SMART And FAST: Test Generation for VLSI Scan-Design Circuits

Authors:
M. Abramovici;J. J. Kulikowski;P. R. Menon;D. T. Miller
Affiliations:
AT&TInformation Systems;AT&TInformation Systems;AT&TInformation Systems;AT&TInformation Systems
Venue:
IEEE Design & Test
Year:
1986

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Abstract

This article describes new concepts and algorithms used to generate tests for VLSI scan-design circuits. The new algorithmsinclude: 1. a low-cost fault-independent algorithm (SMART), 2. a fault-oriented algorithm (FAST), and 3. an algorithm fordynamic test set compaction. The fault-oriented algorithm is guided by new controllability/observability cost functions whoseobjective is to minimize the amount of search done in test generation.