Testing of critical paths for delay faults
Proceedings of the IEEE International Test Conference 2001
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On Generating High Quality Tests for Transition Faults
ATS '02 Proceedings of the 11th Asian Test Symposium
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On Double Transition Faults as a Delay Fault Model
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
SMART And FAST: Test Generation for VLSI Scan-Design Circuits
IEEE Design & Test
Transition path delay faults: a new path delay fault model for small and large delay defects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A deterministic broadside test generation procedure is proposed for transition path delay faults. Under this fault model, a path delay fault is detected if and only if all the individual transition faults along the path are detected by the same test. This is important for detecting both small and large delay defects. To handle the complexity of test generation, the procedure consists of five sub-procedures: a test generation procedure for transition faults, a preprocessing procedure that identifies undetectable transition path delay faults without performing test generation, a fault simulation procedure that identifies transition path delay faults that are detected by the tests for transition faults, a heuristic procedure similar to dynamic test compaction for transition faults that generates tests without backtracking on decisions made for previously detected faults, and a complete branch-and-bound procedure. Experimental results show that for most of the transition path delay faults in benchmark circuits either a test is found or the fault is identified as undetectable.