Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
The DLX Instruction Set Architecture Handbook
The DLX Instruction Set Architecture Handbook
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Evolutionary Test Program Induction for Microprocessor Design Verification
ATS '02 Proceedings of the 11th Asian Test Symposium
Superscalar Processor Validation at the Microarchitecture Level
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Performance and Functional Verification of Microprocessors
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Proceedings of the conference on Design, automation and test in Europe
Code Generation for Functional Validation of Pipelined Microprocessors
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Automatic test program generation for pipelined processors
Proceedings of the 2003 ACM symposium on Applied computing
Fully Automatic Test Program Generation for Microprocessor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
High level validation of next-generation microprocessors
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
An enhanced framework for microprocessor test-program generation
EuroGP'03 Proceedings of the 6th European conference on Genetic programming
Automatic generation of test sets for SBST of microprocessor IP cores
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Efficient techniques for automatic verification-oriented test set optimization
International Journal of Parallel Programming
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
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This paper presents two new march test algorithms, MT-R3CF and MT-R4CF, for detecting reduced 3-coupling and 4-coupling faults, respectively, in n × 1 random-access memories (RAMs). To reduce the length of the tests, only the ...