The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
A compiling genetic programming system that directly manipulates the machine code
Advances in genetic programming
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Evolving Turing-Complete Programs for a Register Machine with Self-modifying Code
Proceedings of the 6th International Conference on Genetic Algorithms
Linear-Graph GP - A New GP Structure
EuroGP '02 Proceedings of the 5th European Conference on Genetic Programming
Evolutionary Test Program Induction for Microprocessor Design Verification
ATS '02 Proceedings of the 11th Asian Test Symposium
Verification of Processor Microarchitectures
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Efficient machine-code test-program induction
CEC '02 Proceedings of the Evolutionary Computation on 2002. CEC '02. Proceedings of the 2002 Congress - Volume 02
Automatic Test Program Generation: A Case Study
IEEE Design & Test
Code Generation for Functional Validation of Pipelined Microprocessors
Journal of Electronic Testing: Theory and Applications
MicroGP—An Evolutionary Assembly Program Generator
Genetic Programming and Evolvable Machines
An enhanced framework for microprocessor test-program generation
EuroGP'03 Proceedings of the 6th European conference on Genetic programming
Feedback-based coverage directed test generation: an industrial evaluation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Coverage-Directed Test Generation Automated by Machine Learning -- A Review
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The continuous advances in microelectronics design are creating a significant challenge to design validation in general, but tackling piplined microprocessors is remarkably more demanding. This paper presents a methodology to automatically induce a test program for a microprocessor maximizing a given verification metric. The approach exploits a new evolutionary algorithm, close to Genetic Programming, able to cultivate effective assembly-language programs. The proposed methodology was used to verify the DLX/pII, an open-source processor with a 5-stage pipeline. Code-coverage was adopted in the paper, since it can be considered the required starting point for any simulation-based functional verification processes. Experimental results clearly show the effectiveness of the approach.