Automatic test program generation for pipelined processors
Proceedings of the 2003 ACM symposium on Applied computing
Fully Automatic Test Program Generation for Microprocessor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
MicroGP—An Evolutionary Assembly Program Generator
Genetic Programming and Evolvable Machines
Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores
Proceedings of the 9th annual conference on Genetic and evolutionary computation
Evolution of synthetic RTL benchmark circuits with predefined testability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An enhanced framework for microprocessor test-program generation
EuroGP'03 Proceedings of the 6th European conference on Genetic programming
Exploiting auto-adaptive µGP for highly effective test programs generation
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Challenges of evolvable hardware: past, present and the path to a promising future
Genetic Programming and Evolvable Machines
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Technology advances allow integrating an entire system on a single chip, including memories and peripherals. The testing of these devices is becoming a major issue for chip manufacturing industries. This paper presents a methodology, similar to genetic programming, for inducing test programs. However, it includes the ability to explicitly specify registers and resorts to directed acyclic graphs instead of trees. Moreover, it exploits a database containing the assembly-level semantics associated with each graph node. This approach is extremely efficient and versatile: candidate solutions are translated into source-code programs allowing millions of evaluations per second. The proposed approach is extremely versatile: the macro library allows the target processor and the environment to be changed easily. The approach was verified on three processors with different instruction sets, different formalisms and different conventions. A complete set of experiments on a test function is also reported for the SPARC processor.