Evolving hardware with genetic learning: a first step towards building a Darwin machine
Proceedings of the second international conference on From animals to animats 2 : simulation of adaptive behavior: simulation of adaptive behavior
A method for generating random circuits and its application to routability measurement
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
Generation of very large circuits to benchmark the partitioning of FPGA
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Hardware Evolution: Automatic Design of Electronic Circuits in Reconfigurable Hardware by Artificial Evolution
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
Overview of Popular Benchmark Sets
IEEE Design & Test
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Aspects of Digital Evolution: Geometry and Learning
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Random Benchmark Circuits with Controlled Attributes
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Analyzing Testability from Behavioral to RT Level
EDTC '97 Proceedings of the 1997 European conference on Design and Test
High-Level Observability for Effective High-Level ATPG
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Evolution of Combinatonial and Sequential On-Line Self-Diagnosing Hardware
EH '03 Proceedings of the 2003 NASA/DoD Conference on Evolvable Hardware
Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers
EH '03 Proceedings of the 2003 NASA/DoD Conference on Evolvable Hardware
A Probabilistic Method for the Computation of Testability of RTL Constructs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Evolvable Components: From Theory to Hardware Implementations
Evolvable Components: From Theory to Hardware Implementations
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
Testability Estimation Based on Controllability and Observability Parameters
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Efficient machine-code test-program induction
CEC '02 Proceedings of the Evolutionary Computation on 2002. CEC '02. Proceedings of the 2002 Congress - Volume 02
FITTest BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
A genetic representation for evolutionary fault recovery in Virtex FPGAs
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Consensus-Based evaluation for fault isolation and on-line evolutionary regeneration
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Generating synthetic benchmark circuits for evaluating CAD tools
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic generation of synthetic sequential benchmark circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthetic circuit generation using clustering and iteration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evolvable Hardware: From Applications to Implications for the Theory of Computation
UC '09 Proceedings of the 8th International Conference on Unconventional Computation
Proceedings of the 13th annual conference companion on Genetic and evolutionary computation
Genetic Programming and Evolvable Machines
Challenges of evolvable hardware: past, present and the path to a promising future
Genetic Programming and Evolvable Machines
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This article presents a new real-world application of evolutionary computing in the area of digital-circuits testing. A method is described which enables to evolve large synthetic RTL benchmark circuits with a predefined structure and testability. Using the proposed method, a new collection of synthetic benchmark circuits was developed. These benchmark circuits will be useful in a validation process of novel algorithms and tools in the area of digital-circuits testing. Evolved benchmark circuits currently represent the most complex benchmark circuits with a known level of testability. Furthermore, these circuits are the largest that have ever been designed by means of evolutionary algorithms. This work also investigates suitable parameters of the evolutionary algorithm for this problem and explores the limits in the complexity of evolved circuits.