Logic block clustering of large designs for channel-width constrained FPGAs
Proceedings of the 42nd annual Design Automation Conference
Evolution of synthetic RTL benchmark circuits with predefined testability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Floating-point FPGA: architecture and modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated model generation for complex systems
MIC '08 Proceedings of the 27th IASTED International Conference on Modelling, Identification and Control
Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09
Static NBTI Reduction Using Internal Node Control
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.03 |
The development of next-generation computer-aided design tools and field programmable gate array architectures require benchmark circuits to experiment with new algorithms and architectures. There has always been a shortage of good public benchmarks for these purposes, and even companies that have access to proprietary customer designs could benefit from designs that meet size and other particular specifications. In this paper, we present a new method of generating realistic synthetic benchmark circuits to help alleviate this shortage. The method significantly improves the quality of previous work by imposing a hierarchy of circuits through clustering and by using a simpler method of characterizing the nature of sequential circuits. Also, in contrast to current constructive generation methods (Hutton et al., 1998), (Hutton et al., 2002), (Darnauer and Dai, 1996), (Iwama and Hino, 1994), (Iwama et al., 1997), (Harlow and Brglez, 1997), (Ghosh et al., 1998), (http://www.cbl.ncsu.edu//-publications //-/#2000-TR@CBL-01-Ghosh), (Pistorius et al., 2000), (Stroobandt et al., 2000), (Verplaetse et al., 2002), we employ new iterative techniques in the generation that provide better control over the generated circuit's characteristics. As in previous work, we assess the realism of the generated circuits by comparing properties of real circuits and generated "clones" of the real circuit after placement and routing. On average, the real and clone circuits' total detailed wirelength differ by only 14%, a major improvement over previous results. In addition, the minimum track count is within 14% and the critical-path delay is within 10%.