FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
The Stratix II logic and routing architecture
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Automatic generation of synthetic sequential benchmark circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthetic circuit generation using clustering and iteration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
The amorphous FPGA architecture
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Timing-driven nonuniform depopulation-based clustering
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Performance-driven dual-rail insertion for chip-level pre-fabricated design
Proceedings of the Conference on Design, Automation and Test in Europe
Net-length-based routability-driven power-aware clustering
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to reduce the amount of inter-cluster connections, hence reducing channel width needs. However, if this exceeds the FPGA's channel width (a hard constraint), then the circuit still cannot be routed. Previous work [11, 12] depopulates logic clusters (CLBs) to reduce channel width. By depopulating non-uniformly, i.e. depopulate more in hard-to-route regions, we show a graceful trade-off between channel width and CLB count. This makes it possible to target specific channel-width constraints during clustering with minimal CLB inflation. Results show channel width decreases of up to 20% with a 5% increase in area. Further decreases of nearly 50% are possible at 3.3 times the original area. Despite the area increase, this technique creates routable solutions from otherwise-unroutable circuits.