Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Directional bias and non-uniformity in FPGA global routing architectures
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
On optimum switch box designs for 2-D FPGAs
Proceedings of the 38th annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
An architectural exploration of via patterned gate arrays
Proceedings of the 2003 international symposium on Physical design
Logic block clustering of large designs for channel-width constrained FPGAs
Proceedings of the 42nd annual Design Automation Conference
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Wire sizing alternative: an uniform dual-rail routing architecture
Proceedings of the conference on Design, automation and test in Europe
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In recent years, pre-fabricated design styles grow up rapidly to amortize the mask cost. However, the interconnection delay of the pre-fabricated design styles slows down the circuit performance due to the high capacitive load. In this paper, we propose a technique to insert dual-rail wires for prefabricated design styles. Furthermore, we propose an effective dual-rail insertion algorithm to reduce the routing area overheads caused by the inserted dual-rail wires. Taking the wire criticality, the delay significance, and the wire congestion into consideration, our proposed algorithm is capable of trading additional routing area overheads for the interconnection performance improvement. The experimental results demonstrate that our proposed algorithm reduces the interconnection delay by 11.4% with 5.8% routing area overheads.