Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Layout Printability Optimization Using a Silicon Simulation Methodology
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Electronics beyond nano-scale CMOS
Proceedings of the 43rd annual Design Automation Conference
A DFM aware, space based router
Proceedings of the 2007 international symposium on Physical design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven dual-rail insertion for chip-level pre-fabricated design
Proceedings of the Conference on Design, Automation and Test in Europe
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To achieve minimum signal propagation delay, the non-uniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploits the wire width flexibilities to trade area for performance. However, many additional design rules, which confine the routing flexibilities, are introduced in nanoscale circuit designs. With the increasing difficulties of fabricating nanoscale circuits, the conventional non-uniform routing architecture becomes clumsy. We propose an uniform dual-rail routing architecture to cope with these new challenges. The proposed architecture exploits the anti-Miller effect between two adjacent wires with the same signal source. Hence, the coupling capacitance between these two wires is reduced. The simulation results demonstrate that our proposed architecture provides a signal propagation channel with similar propagation delay, less crosstalk noise, and less power consumption to the conventional non-uniform routing architecture with moderate routing area overheads. In terms of the properties and the scalabilities, we argue that the uniform dual-rail routing architecture is a wire sizing alternative without incurring layout irregularity and stacked vias overheads.