A Fast Lithography Verification Framework for Litho-Friendly Layout Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Standard Cell Printability Grading and Hot Spot Detection
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Some Thoughts on the IC Design-Manufacture Interface
IEEE Design & Test
Wire sizing alternative: an uniform dual-rail routing architecture
Proceedings of the conference on Design, automation and test in Europe
Total sensitivity based dfm optimization of standard library cells
Proceedings of the 19th international symposium on Physical design
Rapid layout pattern classification
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Leakage reduction through optimization of regular layout parameters
Microelectronics Journal
A novel fuzzy matching model for lithography hotspot detection
Proceedings of the 50th Annual Design Automation Conference
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The manufacturing complexity at the 90nm and 65nm technology nodes severally impacts the design. The traditional use of design rule based verification is no longer a guarantee of high yield once the chip has been manufactured. This paper describes many of the trendsbehind this phenomenon.A new approach to layout that moves from an abstraction approach to a modeling approach is proposed. In this new methodology layouts are processed using resolution enhancement techniques and the results are simulated using lithographical models for a specific manufacturing process. The simulation results are used to identify critical regions in the layouts. The layouts are then optimized based on this analysis to improve their printability, manufacturability and yield.