Low power design flow and libraries
Low power design in deep submicron electronics
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Wire sizing alternative: an uniform dual-rail routing architecture
Proceedings of the conference on Design, automation and test in Europe
A generic standard cell design methodology for differential circuit styles
Proceedings of the conference on Design, automation and test in Europe
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
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In this paper, the impact of the wire grid size on the power-delay-area tradeoff of VLSI digital circuits with differential routing is analyzed. To this aim, the differential MOS current-mode logic (MCML) is adopted as reference logic style, and a complete differential design flow is used. Analysis shows that the choice of the grid size in differential routing has a much stronger impact on the power-delay-area tradeoff, compared to the usual single-ended case. Hence, the grid size is an important knob that must be carefully selected when differential routing is adopted. The dependence of power, delay and area on the grid size is discussed in detail through simple models, and introducing appropriate metrics. To validate the analysis and show basic dependencies in practical circuits, 30 benchmark circuits with an in-house designed MCML cell library were synthesized and routed in 0.18@mm CMOS technology. Results show that non-optimal choice of the grid size can determine a dramatic increase in power (1.7x) and area (1.3x). Interestingly, the grid size that optimizes the power-delay-area tradeoff is almost independent of the specific circuit under design; hence a generally optimum grid size exists that optimizes a very wide range of different circuits.