A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Lightweight Error Correction Coding for System-Level Interconnects
IEEE Transactions on Computers
Analog Integrated Circuits and Signal Processing
CMOS driver-receiver pair for low-swing signaling for low energy on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A charge pump based receiver circuit for voltage scaled interconnect
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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The dense Very Deep Submicron (VDSM) System on Chips (SoC) face a serious limitation in performance due to reverse scaling of global interconnects. Interconnection techniques which decrease delay, delay variation and ensure signal integrity, play an important role in the growth of the semi-conductor industry into future generations. Current-mode low-swing interconnection techniques provide an attractive alternative to conventional full-swing voltage mode signaling in terms of delay, power and noise immunity. In this paper, we present a new current-mode low-swing interconnection technique which reduces the delay and delay variations in global interconnects. Extensive simulations for performance of our circuit under crosstalk, supply voltage, process and temperature variations were performed. The results indicate significant savings in power, reduction in delay and increase in noise immunity compared to other techniques.