CMOS driver-receiver pair for low-swing signaling for low energy on-chip interconnects

Authors:
José C. García Montesdeoca;Juan A. Montiel-Nelson;Saeid Nooshabadi
Affiliations:
Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain;Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain;Department of Information and Communications, Gwangju Institute of Science and Technology, GIST, Gwangju, Republic of Korea
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

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Abstract

This paper describes the design of symmetric low-swing driver-receiver pairs (mj-sib) and (mj-db) for driving signals on the global interconnect lines. The proposed signaling schemes were implemented on 1.0 V 0.13-µm CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire). The mj-sib and mj-db schemes reduce delay by up to 47% and 38% and energy-delay product by up to 34% and 49%, respectively, when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The other key advantages of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This paper also confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.