Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
The design of a low energy FPGA
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Analysis and implementation of charge recycling for deep sub-micron buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Reconfigurable interconnect for next generation systems
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
An Energy Efficient Reconfigurable Public-Key Cryptograhpy Processor Architecture
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
The happy marriage of architecture and application in next-generation reconfigurable systems
Proceedings of the 1st conference on Computing frontiers
FPGA power reduction using configurable dual-Vdd
Proceedings of the 41st annual Design Automation Conference
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
Proceedings of the 2004 international symposium on Low power electronics and design
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Combining low-leakage techniques for FPGA routing design
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Vdd programmability to reduce FPGA interconnect power
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Performance benefits of monolithically stacked 3D-FPGA
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Methodology for high level estimation of FPGA power consumption
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Evaluation of dual VDD fabrics for low power FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Energy-efficient FPGA interconnect design
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Leakage power reduction of embedded memories on FPGAs through location assignment
Proceedings of the 43rd annual Design Automation Conference
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Interconnect and communication synthesis for distributed register-file microarchitecture
Proceedings of the 44th annual Design Automation Conference
Communication-oriented design space exploration for reconfigurable architectures
EURASIP Journal on Embedded Systems
FPGA dynamic power minimization through placement and routing constraints
EURASIP Journal on Embedded Systems
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs
Journal of Signal Processing Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analog Integrated Circuits and Signal Processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Circuits and architectures for field programmable gate array with configurable supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS driver-receiver pair for low-swing signaling for low energy on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switching-Activity directed clustering algorithm for low net-power implementation of FPGAs
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Power dissipation impact of the technology mapping synthesis on look-up table architectures
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A charge pump based receiver circuit for voltage scaled interconnect
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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This paper introduces an energy-efficient FPGA module, intended for embedded implementations. The main features of the proposed cell include a rich local-interconnect network, which drastically reduces the energy dissipated in the wiring, and a dual-voltage scheme that allows pass-transistor networks to operate at low-voltages yet maintain decent performance. Simulations on a benchmark set demonstrate that the proposed module succeeds in its goal of reducing energy consumption by an order of magnitude over existing implementations.