Field-programmable gate arrays
Field-programmable gate arrays
Simultaneous depth and area minimization in LUT-based FPGA mapping
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Re-mapping for low power under tight timing constraints
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Power optimization for FPGA look-up tables
Proceedings of the 1997 international symposium on Physical design
Low-energy embedded FPGA structures
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
The design of a low energy FPGA
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Low-energy FPGAs: architecture and design
Low-energy FPGAs: architecture and design
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Low-power technology mapping for FPGA architectures with dual supply voltages
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power estimation techniques for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
On area/depth trade-off in LUT-based FPGA technology mapping
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a study of the power dissipation repercussion on the logic and physical synthesis using LUT architectures. It is observed that the same function with different mappings on a LUT show different power dissipation. In concrete, the study reveals that the difference depends on the number of inputs of the Boolean function mapped. A power model based on this concept is developed. The power model is used to analyze the efficiency of the synthesis concerning power dissipation in LUTs. Also, a study of the fan-out and the function mapped is done. A power cost model is created to associate the fan-out and our power model. A set of circuits have been synthesized with an academic FPGA synthesis tool. The synthesis tool is used with the options of optimal delay, optimal area and delay-area trade-off. Our study shows that, in this case, synthesizing for area or delay does not affect the power dissipation. Three different LUT architectures have been studied. Results show that a four input LUT is a good choice concerning power dissipation.