Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Xmap: A technology mapper for table-lookup field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
BDD based decomposition of logic functions with application to FPGA synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Acyclic multi-way partitioning of Boolean networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
IEEE Design & Test
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Intellectual property protection by watermarking combinational logic synthesis solutions
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Synthesis for FPGAs with embedded memory blocks
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneous logic decomposition with technology mapping in FPGA designs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A comparing study of technology mapping for FPGA
Proceedings of the conference on Design, automation and test in Europe
Power minization in LUT-based FPGA technology mapping
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Placement-driven technology mapping for LUT-based FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
A new enhanced SPFD rewiring algorithm
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Effective and efficient FPGA synthesis through general functional decomposition
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Power minimization algorithms for LUT-based FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimality study of logic synthesis for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Efficient LUT-based FPGA technology mapping for power minimization
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Combinational and sequential mapping with priority cuts
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Area recovery under depth constraint by cut substitution for technology mapping for LUT-based FPGAs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA area reduction by multi-output function based sequential resynthesis
Proceedings of the 45th annual Design Automation Conference
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Power dissipation impact of the technology mapping synthesis on look-up table architectures
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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In this paper, we present an improvement of the FlowMap algorithm, named CutMap, which combines depth and area minimization during the mapping process by computing min-cost min-height K-feasible cuts for critical nodes for depth minimization and computing min-cost K-feasible cuts for non-critical nodes for area minimization. CutMap guarantees depth-optimal mapping solutions in polynomial time as the FlowMap algorithm but uses considerably fewer K-Luts. We have implemented CutMap and tested it on the MCNC logic synthesis benchmarks. For depth-optimal mapping solutions, CutMap uses 15% fewer K-LUTs than FlowMap. We also tested CutMap followed by the depth relaxation routines in FlowMap_r algorithm, which achieves area minimization by depth relaxation. CutMap followed FlowMap_r performs better than FlowMap_r.