Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Xmap: A technology mapper for table-lookup field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Generalized dominators and post-dominators
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Performance directed technology mapping for look-up table based FPGAs
DAC '93 Proceedings of the 30th international Design Automation Conference
Simultaneous depth and area minimization in LUT-based FPGA mapping
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Power minization in LUT-based FPGA technology mapping
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
IEEE Design & Test
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
DART: delay and routability driven technology mapping for LUT based FPGAs
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
FPGA Technology Mapping for Power Minimization
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Power minimization algorithms for LUT-based FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimality study of logic synthesis for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Improvements to technology mapping for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Area recovery under depth constraint by cut substitution for technology mapping for LUT-based FPGAs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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This work presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT in a significantly shorter time compared to the previous methods. The quality of results is improved by enabling LUT re-implementation and by introducing a cost function which encourages input sharing among LUTs. The experimental results show that, on average, the presented algorithm computes 15.5% and 3.5% smaller LUT mappings compared to the ones obtained by FlowMap and CutMap, respectively, using two orders of magnitude less CPU time. The speed of Hermes makes it suitable for running in an incremental manner during logic synthesis.