Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs

On area/depth trade-off in LUT-based FPGA technology mapping

DAC '93 Proceedings of the 30th international Design Automation Conference

On routability prediction for field-programmable gate arrays

DAC '93 Proceedings of the 30th international Design Automation Conference

A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

An architecture-independent approach to FPGA routing based on multi-weighted graphs

EURO-DAC '94 Proceedings of the conference on European design automation

Simultaneous depth and area minimization in LUT-based FPGA mapping

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

RASP: a general logic synthesis system for SRAM-based FPGAs

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

Combinational logic synthesis for LUT based field programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Low power FPGA design—a re-engineering approach

DAC '97 Proceedings of the 34th annual Design Automation Conference

Technology mapping for FPGAs with embedded memory blocks

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Measuring routing congestion for multi-layer global routing

GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI

Power minization in LUT-based FPGA technology mapping

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping

IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing

Power minimization algorithms for LUT-based FPGA technology mapping

ACM Transactions on Design Automation of Electronic Systems (TODAES)

FPGA technology mapping: a study of optimality

Proceedings of the 42nd annual Design Automation Conference

Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Efficient LUT-based FPGA technology mapping for power minimization

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

On area/depth trade-off in LUT-based FPGA technology mapping

IEEE Transactions on Very Large Scale Integration (VLSI) Systems