Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
On area/depth trade-off in LUT-based FPGA technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
BDD based decomposition of logic functions with application to FPGA synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
FPGA Technology Mapping for Power Minimization
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Exploiting communication complexity for Boolean matching
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
In-place power optimization for LUT-based FPGAs
DAC '98 Proceedings of the 35th annual Design Automation Conference
A re-engineering approach to low power FPGA design using SPFD
DAC '98 Proceedings of the 35th annual Design Automation Conference
Power minization in LUT-based FPGA technology mapping
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Cycle-Accurate Energy Measurement and Characterization of FPGAs
Analog Integrated Circuits and Signal Processing
A high-level clustering algorithm targeting dual Vdd FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power-aware, depth-optimum and area minimization mapping of K-LUT based FPGA circuits
WSEAS Transactions on Computers
Switching-Activity directed clustering algorithm for low net-power implementation of FPGAs
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Sa based power efficient FPGA LUT mapping
Proceedings of the 15th annual conference companion on Genetic and evolutionary computation
| Hi-index | 0.00 |
In this paper, technology mapping algorithmsfor minimizing power consumption in FPGA design are studied.The technology mapping problem for power minimizationhas been shown to be NP-complete.Furthermore, thereare other important objectives, such as the number of PLBs(Programmable Logic Blocks), the number of levels and soon, that should also be optimized simultaneously.We proposea transformational approach in which we start with amapping solution which optimizes certain objective(s) (e.g., the number of PLBs.)The mapping solution is then transformedto reduce the power consumption while keeping thenumber of PLBs fixed.Our algorithm explores the possibilitiesof transforming the functionality of the PLBs so thatthe switching densities of the output edges of the PLBs willbe reduced, leading to a reduction in total power consumption.Our transformational approach can also be viewed as are-engineering approach in which power reduction is achievedthrough re-routing after the PLBs have been placed, utilizingeffectively the capability of a PLB to realize any booleanfunction of up to k variables.