Switching-Activity directed clustering algorithm for low net-power implementation of FPGAs

Authors:
Siobhán Launders;Colin Doyle;Wesley Cooper
Affiliations:
Department of Electronic and Electrical Engineering, University of Dublin, Trinity College, Dublin, Ireland;Department of Electronic and Electrical Engineering, University of Dublin, Trinity College, Dublin, Ireland;Department of Computer Science, University of Dublin, Trinity College, Dublin, Ireland
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

In this paper we present an innovative clustering technique which is combined with a simple tool configuration search aimed at power minimisation in LUT (look-up table)-based FPGAs. The goal of our technique is to reduce the capacitance on high power consuming nets by including as many of these nets as possible inside clusters wherein they can be routed on low capacitance lines. We introduce two new metrics for identifying power critical nets based on the switching activity and the number of net-segments that can be totally absorbed by a cluster. The results of our method show an average reduction of 32.8% with a maximum reduction of 48.9% in the net power over that achieved by Xilinx's ISE 5.3i tools.