Efficient circuit clustering for area and power reduction in FPGAs

Authors:
Amit Singh;Malgorzata Marek-Sadowska
Affiliations:
University of California, Santa Barbara, Santa Barbara, CA;University of California, Santa Barbara, Santa Barbara, CA
Venue:
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Year:
2002

Citing 13
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Abstract

We present a routability-driven bottom-up clustering technique for area and power reduction in clustered FPGAs. This technique uses a cell connectivity metric to identify seeds for efficient clustering. Effective seed selection, coupled with an interconnect-resource aware clustering and placement, can have a favorable impact on circuit routability. It leads to better device utilization, savings in area, and reduction in power consumption. Routing area reduction of 35% is achieved over previously published results. Power dissipation simulations using a buffered pass-transistor-based FPGA interconnect model are presented. They show that our clustering technique can reduce the overall device power dissipation by an average of 13%.