Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic
ISMVL '98 Proceedings of the The 28th International Symposium on Multiple-Valued Logic
Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process
ISMVL '07 Proceedings of the 37th International Symposium on Multiple-Valued Logic
A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future Technologies
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Power modeling and characteristics of field programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new quaternary FPGA based on a voltage-mode multi-valued circuit
Proceedings of the Conference on Design, Automation and Test in Europe
An efficient low power multiple-value look-up table targeting quaternary FPGAs
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
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Field programmable gate arrays usage has been growing steadily for years now. Their popularity stems from the fact that they can be reprogrammed to implement any function, with any amount of parallelism. Unfortunately, exactly due to their flexibility, FPGAs require a huge amount of resources, in the form of LUTs and routing switches, and these can take up to 90% of the chip area. In this paper we present the development of a low-power full CMOS multiple-valued logic to build a LUT for FPGAs. Several circuits are mapped to quaternary LUTs and compared to their binary counterpart. Results show great improvements in terms of area and power consumption. Moreover, we show the positive impact of the proposed architecture in the global reduction of routing switches and wiring, and hence in the total FPGA area.