Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process

Authors:
Motoi Inaba
Affiliations:
Tsukuba University of Technology, Japan
Venue:
ISMVL '07 Proceedings of the 37th International Symposium on Multiple-Valued Logic
Year:
2007

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Abstract

In this paper, the transistor-level layouts and the experiment results of the down literal circuit (DLC) and the analog inverter (AINV) on a CMOS double-polysilicon process are presented. DLC and AINV are the voltage-mode circuits to realize the down literal function with a variable threshold and the inverse function, respectively. Through the experiment of test-production LSI chips, the good transfer characteristics of DLC and AINV are confirmed. For instance, the threshold voltage of DLC is in error by less than 0.03[V] only. AINV achieves the high linearity within 86% of all signal range and the errors of the output voltage are within +0.01[V] and -0.11[V]. The results fully satisfy the requirements for the 5-volt 6-value logic circuits or more. And, the voltage comparator is taken up as an application of DLC and AINV.