Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
SRAM-based FPGA's: testing the LUT/RAM modules
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic
ISMVL '98 Proceedings of the The 28th International Symposium on Multiple-Valued Logic
Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process
ISMVL '07 Proceedings of the 37th International Symposium on Multiple-Valued Logic
A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future Technologies
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Power modeling and characteristics of field programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The use of quaternary logic has been presented as a cost-effective solution to tackle the increasing area and power consumption of million-gate systems. This paper discusses the problem of testing a configurable logic block based on quaternary logic assuming a catastrophic fault model. We then analyze a possible test strategy in terms of number of test configurations and test vectors. Our preliminary results show that, for the most common faults, the resulting test cost for this new design paradigm can be very competitive.