Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems

Authors:
PM Kelly;TM McGinnity;LP Maguire
Affiliations:
Intelligent Systems Engineering Laboratory, Faculty of Engineering, University of Ulster Magee Campus, Derry, Northern Ireland;Intelligent Systems Engineering Laboratory, Faculty of Engineering, University of Ulster Magee Campus, Derry, Northern Ireland;Intelligent Systems Engineering Laboratory, Faculty of Engineering, University of Ulster Magee Campus, Derry, Northern Ireland
Venue:
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Year:
2005

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Abstract

In nano-architectures, transistor counts will place extreme demands on interconnection resources. The chronic problem of interconnect area versus device area will become more acute than it currently is. Even with multi-layering of conductors there may still be attenuation and propagation delay issues which at the extremes of nano-architecture will severely limit performance. When re-configurable devices such as Field Programmable Gate Arrays (FPGAs) are considered the issue of interconnection resources becomes even more acute due to the inherent redundancy already apparent in existing devices. The authors propose the use of a Multiple Valued Signal System to increase functional density whilst reducing the interconnection resource overhead in FPGA based nano-architectures.