Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices
IEEE Transactions on Computers
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Topology Optimization of Interconnection Networks
IEEE Computer Architecture Letters
Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design
ISMVL '07 Proceedings of the 37th International Symposium on Multiple-Valued Logic
CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs
Microelectronics Journal
Power modeling and characteristics of field programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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FPGA structures are widely used as they enable early time-to-market and reduced non-recurring engineering costs in comparison to ASIC designs. Interconnections play a crucial role in modern FPGAs, because they dominate delay, power and area. Multiple-valued logic allows the reduction of the number of interconnections in the circuit, hence can serve as a mean to effectively curtail the impact of interconnections. In this work we propose a new look-up table structure based on a lowpower high-speed quaternary voltage-mode device. The most important characteristics of the proposed architecture are that it is a voltage-mode structure, which allows reduced power consumption, and it is implemented with a standard CMOS technology. Our quaternary implementation overcomes previous proposed techniques with simple and efficient CMOS structures. Moreover, results show significant reductions on power consumption and timing in comparison to binary implementations with similar functionality.