Interband RTDs with nanoelectronic HBT-LED structures for multiple-valued computation
ISMVL '96 Proceedings of the 26th International Symposium on Multiple-Valued Logic
Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Device and circuit simulation of quantum electronic devices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new quaternary FPGA based on a voltage-mode multi-valued circuit
Proceedings of the Conference on Design, Automation and Test in Europe
An efficient low power multiple-value look-up table targeting quaternary FPGAs
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
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This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs). The design is primarily based on a multiple-valued logic literal circuit that utilizes the folded-back I-V (also known as negative differential-resistance, NDR) characteristics of RTDs to compactly implement its gated transfer function. MOS transistors are configured in current-mode logic, where addition of two or more digits is achieved by superimposing the signals of individual wires being physically connected at the summing nodes. The proposed SDFA design uses redundant arithmetic representation and, therefore, the circuit can perform addition of two arbitrary size binary numbers in constant time without the need for either carry propagation or carry look-ahead. The SDFA cell design has been verified through simulation by an augmented SPICE simulator that includes new homotopy-based convergence routines to tackle the nonlinear device characteristics of quantum devices. From the simulation result, the SDFA cell has been found to perform addition operation in 3.5 nanoseconds, which is somewhat superior to other multivalued redundant arithmetic circuits reported in the literature. The SDFA cell requires only 13 MOS transistors and one RTD, as opposed to the state-of-the-art CMOS redundant binary adder requiring 56 transistors, and to the conventional multivalued current-mode adder consisting of 34 MOS transistors. In order to verify the simulation result, a prototype SDFA cell has been fabricated using MOSIS 2-micron CMOS process and GaAs-based RTDs connected externally to the MOSFET circuit.