An efficient low power multiple-value look-up table targeting quaternary FPGAs
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
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Data processing optimization is one of the main concerns for developing of multiple-valued logic. An advantage could be achieved by realization of new functions existing in non-binary logic. These new logic functions could be implemented using quaternary lookup tables. In this work, a quaternary multiplexer circuit is designed to implement any n-variable quaternary logic function based on its truth table. Voltage-mode CMOS with multi-threshold transistors and multi-Vdd quaternary design was suggested. The multiplexer circuit consists of quaternary Down Literal Circuits, binary inverters and binary pass transistor gates. All circuits were simulated with the Spice tool using TSMC 0.18 ìm technology and have shown improvements in performance and power consumption and using less transistors than their equivalent binary circuits.