Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Optimal integer delay budgeting on directed acyclic graphs
Proceedings of the 40th annual Design Automation Conference
A unified theory of timing budget management
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Ant colony metaheuristics for fundamental architectural design problems
Ant colony metaheuristics for fundamental architectural design problems
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Speeding up FPGA placement via partitioning and multithreading
International Journal of Reconfigurable Computing
Multilevel optimization for large-scale hierarchical FPGA placement
Journal of Computer Science and Technology
Timing-driven partitioning-based placement for island style FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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FPGA placement and routing are still challenging problems. Given the increased diversity of logic and routing resources on FPGA chips, it seems appropriate to tackle the placement problem as a mapping between the nodes and edges in a circuit graph to compatible resources in the architecture graph. We explore utilizing graph isomorphism algorithms to perform FPGA placement. We use a hierarchical approach in which the circuit and architecture graphs are simultaneously clustered to reduce the size of the search space, and then a novel reductive graph product method is used to solve the isomorphism problem. The graph product algorithm is called reductive as it eliminates a linear number of candidates at every step of the search process, reducing the number of candidate nodes by approximately 1/3. Compared to the annealing-based placement tool VPR 5.0, we achieve approximately 40% improvement in placement runtime, while improving the critical path delay by about 7% and wire length by 5%, while demanding 1.3% more channels on average.