PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Performance driven multi-layer general area routing for PCB/MCM designs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DUNE: a multi-layer gridless routing system with wire planning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Provably good global routing by a new approximation algorithm for multicommodity flow
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Performance driven multi-level and multiway partitioning with retiming
Proceedings of the 37th Annual Design Automation Conference
An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '78 Proceedings of the 15th Design Automation Conference
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
A New Timing-Driven Multilayer MCM/IC Routing Algorithm
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
A global router with a theoretical bound on the optimal solution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pseudopin assignment with crosstalk noise control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Advanced routing in changing technology landscape
Proceedings of the 2003 international symposium on Physical design
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
Multilevel routing with antenna avoidance
Proceedings of the 2004 international symposium on Physical design
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel full-chip routing with testability and yield enhancement
Proceedings of the 2005 international workshop on System level interconnect prediction
Improved multilevel routing with redundant via placement for yield and reliability
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
A novel framework for multilevel full-chip gridless routing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Multilevel full-chip gridless routing considering optical proximity correction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Probabilistic congestion model considering shielding for crosstalk reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Multilevel routing with jumper insertion for antenna avoidance
Integration, the VLSI Journal
Full-chip multilevel routing for power and signal integrity
Integration, the VLSI Journal
Novel wire density driven full-chip routing for CMP variation control
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Full-chip routing system for reducing Cu CMP & ECP variation
Proceedings of the 21st annual symposium on Integrated circuits and system design
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Multi-layer global routing considering via and wire capacities
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
Integration, the VLSI Journal
A novel wire-density-driven full-chip routing system for CMP variation control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multilevel congestion-based global router
VLSI Design
Multilayer global routing with via and wire capacity considerations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA placement by graph isomorphism (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Extended global routing with RLC crosstalk constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present several novel techniques that make the recently published multilevel routing scheme [19] more effective and complete. Our contributions include: (1) resource reservation for local nets during the coarsening process, (2) congestion-driven, graph-based Steiner tree construction during the initial routing and the refinement process and (3) multi-iteration refinement considering the congestion history. The experiments show that each of these techniques helps to improve the completion rate considerately. Compared to [19], the new routing system reduces the number of failed nets by 2× to 18×, with less than 50% increase in runtime in most cases.