CAD at the design-manufacturing interface
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Advanced routing in changing technology landscape
Proceedings of the 2003 international symposium on Physical design
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Detection of an antenna effect in VLSI designs
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Design Automation for Deepsubmicron: Present and Future
Proceedings of the conference on Design, automation and test in Europe
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem
Proceedings of the conference on Design, automation and test in Europe
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Pattern routing: use and theory for increasing predictability and avoiding coupling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coupling aware timing optimization and antenna avoidance in layer assignment
Proceedings of the 2005 international symposium on Physical design
Improved multilevel routing with redundant via placement for yield and reliability
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
An exact jumper insertion algorithm for antenna effect avoidance/fixing
Proceedings of the 42nd annual Design Automation Conference
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
A novel framework for multilevel full-chip gridless routing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Multilevel full-chip gridless routing considering optical proximity correction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2006 international symposium on Physical design
Proceedings of the 2006 international symposium on Physical design
Optimal jumper insertion for antenna avoidance under ratio upper-bound
Proceedings of the 43rd annual Design Automation Conference
An optimal simultaneous diode/jumper insertion algorithm for antenna fixing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
Integration, the VLSI Journal
Routing for manufacturability and reliability
IEEE Circuits and Systems Magazine
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree
Integration, the VLSI Journal
Proceedings of the International Conference on Computer-Aided Design
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As technology advances into the nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using a built-in jumper insertion approach. Experimental results show that our approach reduced antenna-violated gates by about 98% and also achieved 100% routing completion for all circuits.