The Elmore delay as bound for RC trees with generalized input signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Advanced routing in changing technology landscape
Proceedings of the 2003 international symposium on Physical design
Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Multilevel routing with antenna avoidance
Proceedings of the 2004 international symposium on Physical design
Fitted Elmore delay: a simple and accurate interconnect delay model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coupling aware timing optimization and antenna avoidance in layer assignment
Proceedings of the 2005 international symposium on Physical design
Multilevel routing with jumper insertion for antenna avoidance
Integration, the VLSI Journal
Buffered clock tree sizing for skew minimization under power and thermal budgets
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk- and performance-driven multilevel full-chip routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Antenna avoidance in layer assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An exact zero-skew clock routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Antenna effect is a phenomenon in the plasma-based nanometer process and directly influences the manufacturing yield of VLSI circuits. Because antenna-critical metal wires have sufficient charges to damage the thin gate oxides of the clock input ports connected by a clock tree, the standard cells or IPs cannot be driven by the clock source synchronously. For a given X-architecture clock tree that connects n clock sinks, we consider the antenna effect in the clock tree and propose a discharge-path-based antenna effect detection method. To fix the antenna violations, we use the jumper insertion technique recommended by foundries. Furthermore, we integrate the layer assignment technique to reduce the inserted jumper and via counts. Differing from the existing works, the delay of vias is considered in delay calculation, and a wire sizing technique is applied for clock skew compensation after fixing the antenna violations. Experimental results on benchmarks show that our algorithm runs in O(n^2) to averagely insert 48.21% less jumpers and reduce 20.35% in vias compared with other previous algorithms. Moreover, the SPICE simulation further verifies the correctness of the resulting clock tree.