Discharge-path-based antenna effect detection and fixing for X-architecture clock tree
Integration, the VLSI Journal
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty
Integration, the VLSI Journal
Clock tree resynthesis for multi-corner multi-mode timing closure
Proceedings of the 2014 on International symposium on physical design
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An exact zero-skew clock routing algorithm using the Elmore delay model is presented. The results have been verified with accurate waveform simulation. The authors first review a linear time delay computation method. A recursive bottom-up algorithm is then proposed for interconnecting two zero-skewed subtrees to a new tree with zero skew. The algorithm can be applied to single-staged clock trees, multistaged clock trees, and multi-chip system clock trees. The approach is ideal for hierarchical methods of constructing large systems. All subsystems can be constructed in parallel and independently, then interconnected with exact zero skew. Extensions to the routing of optimum nonzero-skew clock trees (for cycle stealing) and multiphased clock trees are also discussed