Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
TACO: temperature aware clock-tree optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Handling inverted temperature dependence in static timing analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Temperature-insensitive synthesis using multi-vt libraries
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Dynamic thermal clock skew compensation using tunable delay buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffered clock tree sizing for skew minimization under power and thermal budgets
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
SACTA: a self-adjusting clock tree architecture for adapting to thermal-induced delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip thermal modeling based on SPICE simulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Scaling of Temperature-Dependent Effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An exact zero-skew clock routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Matching-based methods for high-performance clock routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Temperature has traditionally been a key parameter to take into account during the many stages of IC design flows, and in particular, during the sign-off phases of critical circuit components like the Clock Distribution Networks (CDNs). While for old technologies this task was accomplished by means of worst case corner-based static analysis, the advent of nanometric CMOS technologies made this approach intrinsically inadequate. This paper provides a detailed analysis of clock skew variations induced by non-uniform thermal profiles on tree-like CDNs. Using a dedicated simulation framework, we characterized the complex thermal effects that metal interconnects and buffers under inverted temperature dependence (ITD) may induce on the clock tree. Experiments conducted on a synthetic, thermal-programmable benchmark underline the presence of unexpected behaviors that standard tools are not able to catch.