On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
In-System Timing Extraction and Control Through Scan-Based, Test-Access Ports
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Clock-tree power optimization based on RTL clock-gating
Proceedings of the 40th annual Design Automation Conference
Predictive dynamic thermal management for multimedia applications
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
A clock-tuning circuit for system-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid Architectural Dynamic Thermal Management
Proceedings of the conference on Design, automation and test in Europe - Volume 1
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors
Proceedings of the 2004 international symposium on Low power electronics and design
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
TACO: temperature aware clock-tree optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Thermal resilient bounded-skew clock tree optimization methodology
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Dynamic management of thermally-induced clock skew: an implementation perspective
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Low-power buffered clock tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gated clock routing for low-power microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Inversed temperature dependence aware clock skew scheduling for sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Thermal-aware clock tree design to increase timing reliability of embedded SoCs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Clock repeater characterization for jitter-aware clock tree synthesis
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Online clock skew tuning for timing speculation
Proceedings of the International Conference on Computer-Aided Design
COOL: control-based optimization of load-balancing for thermal behavior
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty
Integration, the VLSI Journal
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
An efficient method for analyzing on-chip thermal reliability considering process variations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or altering hold/setup constraints, possibly causing the circuit to operate incorrectly. The knowledge of the spatial distribution of temperature can be used to properly design a clock network that is able to compensate such thermal non-uniformities. However, redesign of the clock network is effective only if temperature distribution is stationary, i.e., does not change over time. In this paper, we specifically address the problem of dynamically modifying the clock tree in such a way that it can compensate for temporal variations of temperature. This is achieved by exploiting the buffers that are inserted during the clock network generation, by transforming them into tunable delay elements. Temperature-induced delay variations are then compensated by applying the proper tuning to the tunable buffers, which is computed offline and stored in a tuning table inserted in the design. We propose an algorithm to minimize the number of inserted tunable buffers, as well as their tunable range (which directly relates to complexity). Results show that clock skew is kept within original bounds with worst-case power and area penalty of 3.5% and 5.5%, respectively.