On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Bounded-skew clock and Steiner routing under Elmore delay
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Clock-tree power optimization based on RTL clock-gating
Proceedings of the 40th annual Design Automation Conference
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
Process variation robust clock tree routing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
TACO: temperature aware clock-tree optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Dynamic thermal clock skew compensation using tunable delay buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of thermally robust clock trees using dynamically adaptive clock buffers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low-power buffered clock tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gated clock routing for low-power microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Chip heating and nonuniform distribution of hot and cool zones on the die negatively affect reliability and robustness to failures of nanometer integrated circuits. In fact, signal propagation on interconnects slows down as temperature rises; for long wires crossing regions at different temperatures, such as the clock network, thermally induced delay and skew get altered and may result in timing faults. Failures of this kind are difficult to face due to their transient nature. This paper focuses on clock tree design for the class of embedded systems-on-chip with spatially nonuniform but temporally stationary thermal profiles. We contribute two algorithms for the thermal-aware clock network design that take into account on-chip temperature variations of this nature. The experimental results that we have collected on a number of examples and for different thermal profiles show that, in the presence of on-chip spatial temperature gradients, clock trees designed using a standard methodology incur very significant skew violations, thus originating circuit failures. Instead, clock networks designed using the algorithms presented in this paper always satisfy the initial skew bound.