Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
CMOS Differential and Absolute Thermal Sensors
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Temperature Variable Supply Voltage for Power Reduction
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal Trends in Emerging Technologies
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
TACO: temperature aware clock-tree optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal-aware clock tree design to increase timing reliability of embedded SoCs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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On-chip temperature gradient has emerged as a major design concern for high-performance integrated circuits for the current and future technology nodes. Clock skew is an undesirable phenomenon for synchronous digital circuits that is exacerbated by the temperature difference between various parts of the clock tree. The main aim of this paper is to provide intelligent solution for minimizing the temperature-dependent clock skew by designing dynamically adaptive circuit elements, particularly the clock buffers. Using an RLC model of the clock tree, we investigate the effect of on-chip temperature gradient on the clock skew for a number of temperature profiles that can arise in practice due to different architectures and applications. As an effective way of mitigating the variable clock skew, we present an adaptive circuit technique that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew. Simulation results demonstrate that our adaptive technique is capable of reducing the skew by up to 92.4%, leading to much improved clock synchronization and design performance.