ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Thermal resilient bounded-skew clock tree optimization methodology
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Proceedings of the 43rd annual Design Automation Conference
Dynamic thermal clock skew compensation using tunable delay buffers
Proceedings of the 2006 international symposium on Low power electronics and design
Minimal skew clock embedding considering time variant temperature gradient
Proceedings of the 2007 international symposium on Physical design
Predictions of CMOS compatible on-chip optical interconnect
Integration, the VLSI Journal
Thermally robust clocking schemes for 3D integrated circuits
Proceedings of the conference on Design, automation and test in Europe
Temperature aware task scheduling in MPSoCs
Proceedings of the conference on Design, automation and test in Europe
An analysis of timing violations due to spatially distributed thermal effects in global wires
Proceedings of the 44th annual Design Automation Conference
Integration, the VLSI Journal
Interconnect lifetime prediction for reliability-aware systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature-aware MPSoC scheduling for reducing hot spots and gradients
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Temperature-insensitive synthesis using multi-vt libraries
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Temperature management in multiprocessor SoCs using online learning
Proceedings of the 45th annual Design Automation Conference
Proactive temperature management in MPSoCs
Proceedings of the 13th international symposium on Low power electronics and design
On-chip optical interconnect for reduced delay uncertainty
Proceedings of the 2nd international conference on Nano-Networks
Dynamic thermal clock skew compensation using tunable delay buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proactive temperature balancing for low cost thermal management in MPSoCs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Static and dynamic temperature-aware scheduling for multiprocessor SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Evaluating the effects of temperature gradients and currents nonuniformity in on-chip interconnects
Microelectronics Journal
Predict and act: dynamic thermal management for multi-core processors
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Design of thermally robust clock trees using dynamically adaptive clock buffers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Utilizing predictors for efficient thermal management in multiprocessor SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance and energy efficient cache migrationapproach for thermal management in embedded systems
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
An accurate interconnect thermal model using equivalent transmission line circuit
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic thermal management in 3D multicore architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Thermal-aware clock tree design to increase timing reliability of embedded SoCs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Cool and save: cooling aware dynamic workload scheduling in multi-socket CPU systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Floorplanning for low power IC design considering temperature variations
Microelectronics Journal
Token3D: reducing temperature in 3d die-stacked CMPs through cycle-level power control mechanisms
Euro-Par'11 Proceedings of the 17th international conference on Parallel processing - Volume Part I
Dynamic management of thermally-induced clock skew: an implementation perspective
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Fast timing analysis of clock networks considering environmental uncertainty
Integration, the VLSI Journal
Journal of Electronic Testing: Theory and Applications
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty
Integration, the VLSI Journal
New adaptive encoding schemes for switching activity balancing in on-chip buses
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exploiting thermal coupling information in MPSoC dynamic thermal management
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
Temperature aware thread block scheduling in GPGPUs
Proceedings of the 50th Annual Design Automation Conference
Investigating the effects of inverted temperature dependence (ITD) on clock distribution networks
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
CoMETC: Coordinated management of energy/thermal/cooling in servers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance-driven dynamic thermal management of MPSoC based on task rescheduling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Nonuniform thermal profiles on the substrate in high-performance ICs can significantly impact the performance of global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate. A nonuniform temperature-dependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal nonuniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zero-skew clock-routing methodology is presented. This study suggests that thermally aware analysis should become an integrated part of the various optimization steps in physical-synthesis flow to improve the performance and integrity of signals in global ultra large scale integration interconnects.