CMOS sensors for on-line thermal monitoring of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Analysis of substrate thermal gradient effects on optimal buffer insertion
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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High die temperatures adversely impact CMOS circuit operation degrading performance and reliability of both devices and interconnect. Current thermal scaling trends in multilevel low-k interconnect structures suggest an increasing heat density for the metal layers as a result of which the temperature dependence of logic is matched or often exceeded by that of interconnect. This motivates the need to perform 3-D thermal sensing in deep nanometer designs. We propose a novel sensor design that alleviates the complexities associated with time-to-digital conversion in wire-based thermal sensing. The sensing circuit makes use of wire-segments between individual stages of a ring-oscillator to perform thermal sensing using the oscillator frequency value as the mapping to corresponding wire temperature. Alternatively, the sensor can be tuned to strengthen the thermal sensitivity of the devices over that of interconnects to perform substrate-based sensing. We propose a collaborative scheme to sample the thermal status of the different metal levels and the substrate. The proposed sensor provides a resolution of 1°C while consuming an active power of 65-112µW and its sensitivity to process and supply noise can be minimized through design optimizations.