A heuristic algorithm for the fanout problem
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dynamic power management of complex systems using generalized stochastic Petri nets
Proceedings of the 37th Annual Design Automation Conference
Electrothermal analysis of VLSI systems
Electrothermal analysis of VLSI systems
Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs
Proceedings of the 38th annual Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Self-heating-aware optimal wire sizing under Elmore delay model
Proceedings of the conference on Design, automation and test in Europe
Temperature aware task scheduling in MPSoCs
Proceedings of the conference on Design, automation and test in Europe
Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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This paper studies the effects of the substrate thermal gradients on the buffer insertion techniques. Using a non-uniform temperature-dependent distributed RC interconnect delay model, the buffer insertion problem is analyzed and design guidelines are provided to ensure the near-optimality of the signal performance in the presence of the thermal gradients. In addition, the effect of temperature-dependent driver resistance on the buffer insertion is studied. Experimental results show that neglecting thermal gradients in the substrate and the interconnect lines can result in non-optimal solutions when using standard buffer insertion techniques and that these effects intensify with technology scaling.