Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
RC interconnect synthesis—a moment fitting approach
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Optimal non-uniform wire-sizing under the Elmore delay model
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Optimal wiresizing under the distributed Elmore delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Optimal wire-sizing function with fringing capacitance consideration
DAC '97 Proceedings of the 34th annual Design Automation Conference
Optimal shape function for a bi-directional wire under Elmore delay model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Global interconnect sizing and spacing with consideration of coupling capacitance
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs
Proceedings of the 38th annual Design Automation Conference
Applied Numerical Methods for Engineers and Scientists
Applied Numerical Methods for Engineers and Scientists
Analysis of substrate thermal gradient effects on optimal buffer insertion
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Interconnect thermal modeling for accurate simulation of circuit timing and reliability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An improved Elmore delay model for VLSI interconnects
Mathematical and Computer Modelling: An International Journal
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Global interconnect temperature keeps rising in the current and future technologies due to self-heating and the adiabatic property of top metal layers. The thermal effects impact adversely both reliability and performance of the interconnect wire, shortening the interconnect lifetime and increasing the interconnect delay. Such effects must be considered during the process of interconnect design. In this paper, one important argument is that the traditional linear dependence between wire resistance and wire width is no longer adequate for high layer interconnects due to the adiabatic property of these wires. By using curve fitting technique, we propose a quadratic model to represent the resistance of interconnect, which is aware of the thermal effects. Based on this model and the Elmore delay model, we derived a linear optimal wire sizing formula in form of f (x) = ax + b. Compared to non-thermal-aware exponential wire sizing formula in form of f (x) = ae-bx, we observed a 49.7% average delay gain with different choices of physical parameters.