Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal non-uniform wire-sizing under the Elmore delay model
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Shaping a VLSI Wire to Minimize Elmore Delay
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Optimal Wire-Sizing Function with Fringing Capacitance Consideration
Optimal Wire-Sizing Function with Fringing Capacitance Consideration
A new approach to simultaneous buffer insertion and wire sizing
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Optimal shape function for a bi-directional wire under Elmore delay model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Shaping a VLSI wire to minimize delay using transmission line model
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Wire-sizing for delay minimization and ringing control using transmission line model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A graph based algorithm for optimal buffer insertion under accurate delay models
Proceedings of the conference on Design, automation and test in Europe
A polynomial time optimal algorithm for simultaneous buffer and wire sizing
Proceedings of the conference on Design, automation and test in Europe
A fast and accurate delay estimation method for buffered interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fitted Elmore delay: a simple and accurate interconnect delay model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire sizing with scattering effect for nanoscale interconnection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Process variation robust clock tree routing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Wire shaping of RLC interconnects
Integration, the VLSI Journal
Self-heating-aware optimal wire sizing under Elmore delay model
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2009 international symposium on Physical design
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In this paper, we consider non-uniform wire-sizing under theElmore delay model.Given a wire segment of length L, letf(x) be the width of the wire at position x, 0 驴 x 驴 L.It was shown in [Optimal Wire-sizing formula under the Elmore delay model, Shaping a distributed-RC line to minimize Elmore delay] that the optimal wire-sizing functionwhich minimizes delay is an exponential tapering functionf(x) = ae{-bx}, where a 0 and b 0 are constants.Unfortunately, [Optimal Wire-sizing formula under the Elmore delay model, Shaping a distributed-RC line to minimize Elmore delay] did not consider fringing capacitancewhich is at least comparable in size to area capacitance indeep submicron designs.As a result, exponential taperingis no longer the optimal strategy.In this paper, we showthat the optimal wire-sizing function, taking fringing capacitanceinto consideration, is f(x) = \frac{{ - c_f }}{{2c_0 }}(\frac{1}{{W(\frac{{ - c_f }}{{ae^{ - bx} }})}} + 1) whereW(x) = \sum\nolimits_{n = 1}^\infty{\frac{{( - n)^{n - 1} }}{{n!}}} x^n is the Lambert's W function, c{f}and c{0} are the respective fringing capacitance and area capacitanceof wire per unit square, a 0 and b 0 are constants.The optimal wire-sizing function degenerates into an exponentialtapering function as c}{f} = 0, and degenerates into asquare-root tapering function (f(x)=\sqrt {b - ax}, where a 0and b 0) as c{f} 驴 驴.Our experimental results show thatthe optimal wire-sizing function can significantly reduce theinterconnection delay of exponentially tapered wires.In thecase where lower and upper bounds on the wire widths aregiven, the optimal wire-sizing function is a truncated versionof the above function.Finally, our optimal wire-sizing functioncan be iteratively applied to optimally size all the wiresegments in a routing tree for objectives such as minimizingweighted sink delay, minimizing maximum sink delay, orminimizing area subject to delay bounds at the sinks.