Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Optimal equivalent circuits for interconnect delay calculations using moments
EURO-DAC '94 Proceedings of the conference on European design automation
Exact moment matching model of transmission lines and application to interconnect delay estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Introduction to Maple (2nd ed.)
Introduction to Maple (2nd ed.)
Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An explicit RC-circuit delay approximation based on the first three moments of the impulse response
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal wire-sizing function with fringing capacitance consideration
DAC '97 Proceedings of the 34th annual Design Automation Conference
A new approach to simultaneous buffer insertion and wire sizing
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
Shaping a VLSI wire to minimize delay using transmission line model
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Delay Models for MCM Interconnects when Response is Non-Monotone
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
A graph based algorithm for optimal buffer insertion under accurate delay models
Proceedings of the conference on Design, automation and test in Europe
Wire shaping of RLC interconnects
Integration, the VLSI Journal
Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
| Hi-index | 0.00 |
In this paper, we present a fast and accurate delay estimation method for buffered interconnects. The interconnect wire is modeled by the transmission line model which is more accurate and efficient than lumped circuit model. For the interconnect wire, we specify the wire shape to be of the form f(x) = ae-bx. Note that if we let b = 0, our work is reduced to uniform wire case. By using first three poles in the transfer function, we derive analytical expressions for calculating delay at any threshold voltage under a finite ramp input. The expressions involved in calculating coefficients in the transfer function are also analytical. We use k-factor equations to estimate delays for buffers. Since the k-factor equations require a loading capacitance for delay computation, we use the effective capacitance technique introduced in [17] to calculate the effective capacitance for each interconnect wire which is connected to a buffer. Therefore, our delay calculation for buffered interconnects is analytical and thus very efficient. Our experiments show that signal waveforms estimated by our method are very close to SPICE's results.