Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Exact moment matching model of transmission lines and application to interconnect delay estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal wire-sizing function with fringing capacitance consideration
DAC '97 Proceedings of the 34th annual Design Automation Conference
A new approach to simultaneous buffer insertion and wire sizing
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A fast and accurate delay estimation method for buffered interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Delay Models for MCM Interconnects when Response is Non-Monotone
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Wire-sizing optimization with inductance consideration using transmission-line model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for identifying good buffer insertion candidate locations
Proceedings of the 2004 international symposium on Physical design
An exact algorithm for the statistical shortest path problem
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Buffer insertion under process variations for delay minimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Low-power repeater insertion with both delay and slew rate constraints
Proceedings of the 43rd annual Design Automation Conference
Path smoothing via discrete optimization
Proceedings of the 45th annual Design Automation Conference
Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Buffer design and optimization for lut-based structured ASIC design styles
Proceedings of the 19th ACM Great Lakes symposium on VLSI
An efficient low-power buffer insertion with time and area constraints
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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