Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Static power optimization of deep submicron CMOS circuits for dual VT technology
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
FSMD functional partitioning for low power
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Low-power task scheduling for multiple devices
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
A graph based algorithm for optimal buffer insertion under accurate delay models
Proceedings of the conference on Design, automation and test in Europe
Function and Architecture Optimization and Co-Design of Embedded Systems
Function and Architecture Optimization and Co-Design of Embedded Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Design and selection of buffers for minimum power-delay product
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Efficient Power Estimation Techniques for HW/SW Systems
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
An efficient surface-based low-power buffer insertion algorithm
Proceedings of the 2005 international symposium on Physical design
Proceedings of the 42nd annual Design Automation Conference
Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
FSM re-engineering and its application in low power state encoding
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Exploring "temperature-aware" design in low-power MPSoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
HybDTM: a coordinated hardware-software approach for dynamic thermal management
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the Conference on Design, Automation and Test in Europe
Architectural synthesis for DSP silicon compilers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Technology scaling has resulted in interconnect delay increasing significantly. Buffer-insertion is a well-known technique to reduce wire delays of critical signal nets in a circuit. However, the power consumption of buffers has become a critical concern with the increase of the number of buffers. Thanks to a genetic-based algorithm, our work addresses the interconnect delay problem while meeting power and area constraints.