Static power optimization of deep submicron CMOS circuits for dual VT technology

Mixed-Vth (MVT) CMOS circuit design methodology for low power applications

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Monotonic static CMOS and dual-VT technology

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

A static power model for architects

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

Minimizing stand-by leakage power in static CMOS circuits

Proceedings of the conference on Design, automation and test in Europe

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

Proceedings of the 38th annual Design Automation Conference

Design methodology and optimization strategy for dual-VTH scheme using commercially available tools

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

Proceedings of the 39th annual Design Automation Conference

Optimizing Static Power Dissipation by Functional Units in Superscalar Processors

CC '02 Proceedings of the 11th International Conference on Compiler Construction

Standby power optimization via transistor sizing and dual threshold voltage assignment

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Leakage Power Analysis and Reduction during Behavioral Synthesis

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

An ASIC design methodology with predictably low leakage, using leakage-immune standard cells

Proceedings of the 2003 international symposium on Low power electronics and design

Simultaneous Vt selection and assignment for leakage optimization

Proceedings of the 2003 international symposium on Low power electronics and design

Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization

Proceedings of the 2003 international symposium on Low power electronics and design

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

Statistical analysis of subthreshold leakage current for VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

LECTOR: a technique for leakage reduction in CMOS circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Leakage power minimization for the synthesis of parallel multiplier circuits

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Statistical optimization of leakage power considering process variations using dual-Vth and sizing

Proceedings of the 41st annual Design Automation Conference

A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

An efficient algorithm for statistical minimization of total power under timing yield constraints

Proceedings of the 42nd annual Design Automation Conference

Probabilistic dual-Vth leakage optimization under variability

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design

Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case Study

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Statistical technology mapping for parametric yield

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

A predictably low-leakage ASIC design style

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Minimizing leakage power of sequential circuits through mixed-Vt flip-flops and multi-Vt combinational gates

ACM Transactions on Design Automation of Electronic Systems (TODAES)

DFT and minimum leakage pattern generation for static power reduction during test and burn-in

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

An efficient low-power buffer insertion with time and area constraints

ICC'10 Proceedings of the 14th WSEAS international conference on Circuits

A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Simultaneous Vtselection and assignment for leakage optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Leakage and dynamic glitch power minimization using integer linear programming for vth assignment and path balancing

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Combined heuristics for synthesis of SOCs with time and power constraints

Computers and Electrical Engineering