Leakage and dynamic glitch power minimization using integer linear programming for vth assignment and path balancing

Authors:
Yuanlin Lu;Vishwani D. Agrawal
Affiliations:
Department of ECE, Auburn University, Auburn, AL;Department of ECE, Auburn University, Auburn, AL
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

This paper presents a novel technique, which uses integer linear programming (ILP) to minimize the leakage power in a dual-threshold static CMOS circuit by optimally placing high-threshold devices and simultaneously reduces the glitch power using the smallest number of delay elements to balance path delays. The constraint set size for the ILP model is linear in the circuit size. Experimental results show 96%, 40% and 70% reduction of leakage, dynamic and total power, respectively, for the benchmark circuit C7552 implemented in the 70nm BPTM CMOS technology.