An Empirical and Analytical Comparison of Delay Elements and a New Delay Element Design

Authors:
Nihar R. Mahapatra;Alwin Tareen;Sriram V. Garimella
Affiliations:
-;-;-
Venue:
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Year:
2000

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Abstract

This paper comprehensively reviews five different delay element architectures for use in CMOS VLSI design. The first four delay elements that we analyze are already in general use; they are the transmission gate, cascaded inverters, thyristor, and voltage-controlled delay element. The fifth delay element, a transmission gate with Schmitt trigger, is a new architecture that we are proposing in this paper. We compare these delay elements, both analytically and through simulations, in terms of four important parameters: delay, signal integrity, power consumption, and area, and find that they have widely varying characteristics. Depending upon the delay value required in an application, results presented in this paper will enable a designer to select the most appropriate delay element that meets signal integrity, power consumption, and area specifications.